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240pin DDR3L SDRAM Registered DIMM
DDR3L SDRAM Registered DIMM Based on 2Gb B-die
HMT325R7BFR8A HMT351R7BFR8A HMT351R7BFR4A HMT31GR7BFR8A HMT31GR7BFR4A HMT42GR7BMR4A
*Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 0.2 / Feb. 2010
1
Revision History
Revision No. 0.1 0.2 History Initial Release Added IDD Specification Draft Date Jan. 2010 Feb. 2010 Remark Preliminary Preliminary
Rev. 0.2 / Feb. 2010
2
Description
Hynix Registered DDR3 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations.
Features
* * * * * * * * * * * * * Power Supply: VDD=1.35V (1.283V to 1.45V) VDDQ = 1.35V (1.283V to 1.45V) Backward Compatible with 1.5V DDR3 Memory Module VDDSPD=3.0V to 3.6V Functionality and operations comply with the DDR3L SDRAM datasheet 8 internal banks Data transfer rates: PC3L-10600, PC3L-8500 Bi-Directional Differential Data Strobe 8 bit pre-fetch Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop) Supports ECC error correction and detection On-Die Termination (ODT) Temperature sensor with integrated SPD
* This product is in compliance with the RoHS directive.
Ordering Information
Part Number HMT325R7BFR8A-G7/H9 HMT351R7BFR8A-G7/H9 HMT351R7BFR4A-G7/H9 HMT31GR7BFR8A-G7/H9 HMT31GR7BFR4A-G7/H9 HMT42GR7BMR4A-G7/H9 Density 2GB 4GB 4GB 8GB 8GB 16GB Organization 256Mx72 512Mx72 512Mx72 1Gx72 1Gx72 2Gx72 Component Composition 256Mx8(H5TC2G83BFR)*9 256Mx8(H5TC2G83BFR)*18 512Mx4(H5TC2G43BFR)*18 256Mx8(H5TC2G83BFR)*36 512Mx4(H5TC2G43BFR)*36 DDP 1Gx4(H5TC4G43BMR)*36 # of ranks 1 2 1 4 2 4 FDHS X X X O O O
* In order to uninstall FDHS, please contact sales administrator
Rev. 0.2 / Feb. 2010 3
Key Parameters
MT/s DDR3-1066 DDR3-1333 Grade -G7 -H9 tCK (ns) 1.875 1.5 CAS Latency (tCK) 7 9 tRCD (ns) 13.125 13.5 tRP (ns) 13.125 13.5 tRAS (ns) 37.5 36 tRC (ns) 50.625 49.5 CL-tRCD-tRP 7-7-7 9-9-9
Speed Grade
Frequency [MHz] Grade CL6 -G7 -H9 800 800 CL7 1066 1066 CL8 1066 1066 1333 1333 CL9 CL10 Remark
Address Table
2GB(1Rx8) Refresh Method Row Address Column Address Bank Address Page Size 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 4GB(2Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 4GB(1Rx4) 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 8GB(4Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 8GB(2Rx4) 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 16GB(4Rx4) 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB
Rev. 0.2 / Feb. 2010
4
Pin Descriptions
Pin Name CK0 CK0 CK1 CK1 CKE[1:0] RAS Description Clock Input, positive line Clock Input, negative line Clock Input, positive line Clock Input, negative line Clock Enables Row Address Strobe Num ber 1 1 1 1 2 1 Pin Name ODT[1:0] DQ[63:0] CB[7:0] DQS[8:0] DQS[8:0] DM[8:0]/ DQS[17:9], TDQS[17:9] DQS[17:9], TDQS[17:9] EVENT TEST RESET VDD VSS VREFDQ VREFCA VTT VDDSPD Description On Die Termination Inputs Data Input/Output Data check bits Input/Output Data strobes Data strobes, negative line Data Masks / Data strobes, Termination data strobes Data strobes, negative line, Termination data strobes Reserved for optional hardware temperature sensing Memory bus test tool (Not Connected and Not Usable on DIMMs) Register and SDRAM control pin Power Supply Ground Reference Voltage for DQ Reference Voltage for CA Termination Voltage SPD Power Num ber 2 64 8 9 9 9
CAS WE S[3:0] A[9:0],A11, A[15:13] A10/AP A12/BC BA[2:0] SCL SDA SA[2:0] Par_In Err_Out
Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge Address Input/Burst chop SDRAM Bank Addresses Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs Parity bit for the Address and Control bus Parity error found on the Address and Control bus
1 1 4 14 1 1 3 1 1 3 1 1
9 1 1 1 22 59 1 1 4 1
Rev. 0.2 / Feb. 2010
5
Input/Output Functional Descriptions
Symbol
CK0 CK0 CK1 CK1
Type
IN IN IN IN
Polarity
Positive Line Negative Line Positive Line Negative Line Active High
Function
Positive line of the differential pair of system clock inputs that drives input to the onDIMM Clock Driver. Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver. Terminated but not used on RDIMMs. Terminated but not used on RDIMMs. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the command decoders for the associated rank of SDRAM when low and disables decoders when high. When decoders are disabled, new commands are ignored and previous operations continue. Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s). For modules with two registers, S[3:2] operate similarly to S[1:0] for the second set of register outputs or register control words. On-Die Termination control signals When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Reference voltage for DQ0-DQ63 and CB0-CB7. Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1. Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines mode register is to be accessed during an MRS cycle. Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8 identification for `'BL on the fly'' during CAS command. The address inputs also provide the op-code during Mode Register Set commands. Data and Check Bit Input/Output pins Masks write data when high, issued concurrently with input data. Power and ground for the DDR SDRAM input buffers and core logic. Termination Voltage for Address/Command/Control/Clock nets.
CKE[1:0]
IN
S[3:0]
IN
Active Low
ODT[1:0] RAS, CAS, WE VREFDQ VREFCA
IN IN Supply Supply
Active High Active Low
BA[2:0]
IN
--
A[15:13, 12/BC,11, 10/AP,[9:0]
IN
--
DQ[63:0], CB[7:0] DM[8:0] VDD, VSS VTT
I/O IN Supply Supply
-- Active High
Rev. 0.2 / Feb. 2010
6
Symbol
DQS[17:0] DQS[17:0]
Type
I/O I/O
Polarity
Positive Edge Negative Edge
Function
Positive line of the differential data strobe for input and output data. Negative line of the differential data strobe for input and output data. TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1
TDQS[17:9] TDQS[17:9]
OUT
SA[2:0]
IN
--
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
SDA
I/O
--
SCL
IN OUT (open drain) Supply IN IN OUT (open drain)
--
EVENT
This signal indicates that a thermal event has been detected in the thermal sensing device.The system should guarantee the electrical level requirement is met for the Active Low EVENT pin on TS/SPD part. No pull-up resister is provided on DIMM. Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. Parity bit for the Address and Control bus. ("1 ": Odd, "0 ": Even) Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out bus line to VDD on the system planar to act as a pull up. Used by memory bus analysis tools (unused (NC) on memory DIMMs)
VDDSPD RESET Par_In Err_Out TEST
Rev. 0.2 / Feb. 2010
7
Pin Assignments
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Front Side (left 1-60)
VREFDQ VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25
Pin #
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151
Back Side (right 121-180)
VSS DQ4 DQ5 VSS DM0,DQS9, TDQS9 NC,DQS9, TDQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1,DQS10, TDQS10 NC,DQS10, TDQS10 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2,DQS11, TDQS11 NC,DQS11, TDQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS
Pin #
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
Front Side (left 61-120)
A2 VDD NC, CK1 NC, CK1 VDD VDD VREFCA Par_In, NC VDD A10 / AP BA0 VDD WE CAS VDD S1, NC ODT1, NC VDD S2, NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41
Pin #
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211
Back Side (right 181-240)
A1 VDD VDD CK0 CK0 VDD EVENT, NC A0 VDD BA1 VDD RAS S0 VDD ODT0 A13 VDD S3, NC VSS DQ36 DQ37 VSS DM4,DQS13, TDQS13 NC,DQS13, TDQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS
NC = No Connect; RFU = Reserved Future Use
Rev. 0.2 / Feb. 2010
8
Pin #
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Front Side (left 1-60)
VSS DQS3 DQS3 VSS DQ26 DQ27 VSS CB0, NC CB1, NC VSS DQS8 DQS8 VSS CB2, NC CB3, NC VSS VTT, NC KEY
Pin #
152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Back Side (right 121-180)
DM3,DQS12, TDQS12 NC,DQS12, TDQS12 VSS DQ30 DQ31 VSS CB4, NC CB5, NC VSS NC,DM8,DQS17, TDQS17 NC,DQS17, TDQS17 VSS CB6, NC CB7, NC VSS NC(TEST) RESET KEY
Pin #
92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Front Side (left 61-120)
VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT
Pin #
212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Back Side (right 181-240)
DM5,DQS14, TDQS14 NC,DQS14, TDQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6,DQS15, TDQS15 NC,DQS15, TDQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7,DQS16, TDQS16 NC,DQS16, TDQS16 VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT
49 50 51 52 53 54 55 56 57 58 59 60
VTT, NC CKE0 VDD BA2 Err_Out, NC VDD A11 A7 VDD A5 A4 VDD
169 170 171 172 173 174 175 176 177 178 179 180
CKE1, NC VDD A15 A14 VDD A12 / BC A9 VDD A8 A6 VDD A3
NC = No Connect; RFU = Reserved Future Use
Rev. 0.2 / Feb. 2010
9
Registering Clock Driver Specifications
Capacitance Values
Symbol Parameter Input capacitance, Data inputs CI Input capacitance, CK, CK, FBIN, FBIN Input capacitance, CK, CK, FBIN, FBIN (DDR3-1600) CIR Input capacitance, RESET, MIRROR, QCSEN VI = VDD or GND; VDD = 1.5v Conditions Min 1.5 2 1.5 Typ Max 2.5 3 2.5 3 Unit pF pF pF pF
Input & Output Timing Requirements
DDR3-800 1066/1333 Min fclock fTEST tSU tH tPDM tDIS tEN Input clock frequency Input clock frequency Setup time Hold time Propagation delay, singlebit switching Output disable time (1/2Clock prelaunch) Output enable time (1/2Clock prelaunch) Application frequency Test frequency Input valid before CK/CK Input to remain valid after CK/CK CK/CK to output Yn/Yn to output float Output driving to Yn/Yn 300 70 100 175 0.65 0.5 tCK + tQSK1(min) 0.5 tCK tQSK1(max) Max 670 300 1.0 Mhz Mhz ps ps ns ps ps
Symbol
Parameter
Conditions
Unit
Rev. 0.2 / Feb. 2010
10
On DIMM Thermal Sensor
The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor comply with JEDEC "TSE2002av, Serial Presence Detect with Temperature Sensor".
Connection of Thermal Sensor
EVENT SCL SDA SA0 SA1 SA2 SA0 SPD with SA1 Integrated SA2 TS
EVENT SCL SDA
Temperature-to-Digital Conversion Performance
Parameter Condition Active Range, 75C < TA < 95C Temperature Sensor Accuracy (Grade B) Monitor Range, 40C < TA < 125C -20C < TA < 125C Min Typ 0.5 1.0 2.0 Max 1.0 2.0 3.0 Unit C C C C
Resolution
0.25
Rev. 0.2 / Feb. 2010
11
Functional Block Diagram
A[N:O]A /BA[N:O]A A[N:O]B /BA[N:O]B ZQ
2GB, 256Mx72 Module(1Rank of x8)
RODT0A RS0B RRASB RS0A RRASA RODT0B ODT ODT PCK0A RCKE0A PCK0B RCKE0B CK CKE CK CKE RCASA RCASB PCK0A PCK0B RWEA RWEB
A[N:O]/BA[N:O]
D8
ODT CK CKE WE CK
D4
WE CK
A[O:N]/BA[N:O]
D3
ODT CK CKE WE CK
D5
WE CK
RAS
CAS
CS
A[O:N]/BA[N:O]
D2
ODT CK CKE WE CK
D6
ODT CK CKE WE CK
RAS
CAS
CS
A[N:O]/BA[N:O]
D1
ODT CK CKE WE CK
D7
ODT CK CKE WE CK
A[N:O]/BA[N:O]
DQS1 DQS1 DM1/DQS10 DQS10 DQ[15:8]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
ZQ
DQS7 DQS7 DM7/DQS16 DQS16 DQ[63:56]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
A[O:N]/BA[N:O]
ZQ
DQS2 DQS2 DM2/DQS11 DQS11 DQ[23:16]
DQS DQS TDQS TDQS DQ [7:0]
ZQ
DQS6 DQS6 DM6/DQS15 DQS15 DQ[55:48]
DQS DQS TDQS TDQS DQ [7:0]
RAS
CAS
CS
A[O:N]/BA[N:O] ZQ
DQS3 DQS3 DM3/DQS12 DQS12 DQ[31:24]
DQS DQS TDQS TDQS DQ [7:0]
ZQ
DQS5 DQS5 DM5/DQS14 DQS14 DQ[47:40]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
A[O:N]/BA[O:N] ZQ
DQS8 DQS8 DM8/DQS17 DQS17 CB[7:0]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
ZQ
DQS4 DQS4 DM4/DQS13 DQS13 DQ[39:32]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
VDDSPD VDD VTT VREFCA VREFDQ VSS
SPD
D0-D8
D0-D8 D0-D8 D0-D8
D0
ODT CK CKE WE CK
A[N:O]/BA[N:O]
DQS0 DQS0 DM0/DQS9 DQS9 DQ[7:0]
DQS DQS TDQS TDQS DQ [7:0] RAS CAS CS
ZQ
Vtt
Note:
1.DQ-to-I/O wiring may be changed within byte. 2.ZQ resistors are 240 1%.For all other resistor values refer to the appropriate wiring diagram.
Vtt
S0 S1 BA[N:0] A[N:0] RAS CAS WE CKE0 ODT0 CK0 CK0 CK0 CK0 PAR_IN
120 1% 120 1%
1: 2 R E G I S T E R / P L L
OERR RST
RS0A CS0: SDRAMs D[3:0], D8 RS0B CS0: SDRAMs D[7:4] RBA[N:0]A BA[N:0]: SDRAMs D[3:0], D8 RBA[N:0]A BA[N:0]: SDRAMs D[7:4] RA[N:0]A A[N:0]: SDRAMs D[3:0], D8 RA[N:0]A A[N:0]: SDRAMs D[7:4] RRASA RAS: SDRAMs D[3:0], D8 RRASA RAS: SDRAMs D[7:4] RCASA CAS: SDRAMs D[3:0], D8 RCASA CAS: SDRAMs D[7:4] RWEA WE: SDRAMs D[3:0], D8 RWEA WE: SDRAMs D[7:4] RCKE0A CKE0: SDRAMs D[3:0], D8 RCKE0B CKE0: SDRAMs D[7:4] RODT0A ODT0: SDRAMs D[3:0], D8 RODT0B ODT0: SDRAMs D[7:4] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] Err_Out
VDDSPD EVENT SCL SDA
VDDSPD
SA0
SA0 SA1 SA2 VSS
EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
RST: SDRAMs D[8:0] S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330 resistor to ground
RESET
Rev. 0.2 / Feb. 2010
12
4GB, 512Mx72 Module(2Rank of x8) - page1
A[N:O]A /BA[N:O]A RODT1A A[N:O]B /BA[N:O]B RODT0A RODT0B PCK0A RCKE0A PCK0B RCKE0B RODT1B
A[O:N]/BA[N:O] ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] ODT
PCK1A RCKE1A
RS1A
A[N:O]/BA[N:O]
D8
ODT CAS CK CKE WE CK
A[N:O]/BA[N:O]
D17
ODT CAS CK CKE WE CK
D4
ODT CAS CK CKE WE CK
A[N:O]/BA[N:O]
DQS8 DQS8 DM8/DQS17 DQS17 CB[7:0]
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS4 DQS4 DM4/DQS13 DQS13 DQ[39:32]
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS DQS TDQS TDQS DQ [7:0]
RAS CAS WE WE WE WE
RS1B
D13
CK CKE CK CKE CK CKE CK CKE CK CK CK CK
ZQ
CS
ZQ
CS
ZQ
CS
ZQ
CS
A[N:O]/BA[N:O]
D3
ODT CK CKE CAS WE CK
A[N:O]/BA[N:O]
D12
ODT CAS CK CKE WE CK
D5
ODT CK CKE CAS WE CK
A[N:O]/BA[N:O]
DQS3 DQS3 DM3/DQS12 DQS12 DQ[31:24]
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS5 DQS5 DM5/DQS14 DQS14 DQ[47:40]
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS DQS TDQS TDQS DQ [7:0]
RAS CAS
D14
ZQ
CS
ZQ
CS
ZQ
CS
ZQ
CS
A[N:O]/BA[N:O]
D2
ODT CAS CK CKE WE CK
A[N:O]/BA[N:O]
D11
ODT CK CKE CAS WE CK
D6
ODT CAS CK CKE WE CK
A[N:O]/BA[N:O]
DQS2 DQS2 DM2/DQS11 DQS11 DQ[23:16]
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS6 DQS6 DM6/DQS15 DQS15 DQ55:48]
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS DQS TDQS TDQS DQ [7:0]
RAS CAS
D15
ZQ
CS
ZQ
CS
ZQ
CS
ZQ
CS
A[O:N]/BA[N:O]
D1
ODT CAS CK CKE WE CK
A[O:N]/BA[N:O]
D10
ODT CAS CK CKE WE CK
D7
ODT CAS CK CKE WE CK
A[N:O]/BA[N:O]
DQS1 DQS1 DM1/DQS10 DQS10 DQ[15:8]
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS7 DQS7 DM7/DQS16 DQS16 DQ[63:56]
DQS DQS TDQS TDQS DQ [7:0]
RAS
DQS DQS TDQS TDQS DQ [7:0]
RAS CAS
D16
ZQ
CS
ZQ
CS
ZQ
CS
ZQ
CS
A[N:O]/BA[N:O]
D0
ODT CAS CK CKE WE CK
D9
ODT CK CKE CAS WE CK
RAS
RAS
ZQ
CS
ZQ
CS
A[N:O]/BA[N:O]
DQS0 DQS0 DM0/DQS9 DQS9 DQ[7:0]
DQS DQS TDQS TDQS DQ [7:0]
DQS DQS TDQS TDQS DQ [7:0]
Vtt
VDDSPD EVENT
Vtt
VDDSPD
SA0
SCL SDA
EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA
Note: 1. DQ-to-I/O wiring may be changed within a byte. 2. Unless otherwise noted, resistor values are 15 5%. 3. ZQ resistors are 240 1%. For all other resistor values refer to the appropriate wiring diagram. 4. See the wiring diagrams for all resistors associated with the command, address and control bus.
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
VDDSPD VDD VTT VREFCA VREFDQ VSS
Serial PD
D0-D17 D0-D17 D0-D17 D0-D17 D0-D17
Rev. 0.2 / Feb. 2010
PCK1B RCKE1B
RCASA
RS0A RRASA
RS0B RRASB
RCASB
PCK0A
PCK1A
PCK0B
RWEA
RWEB
PCK1B
SA0 SA1 SA2 VSS
13
4GB, 512Mx72 Module(2Rank of x8) - page2
S0 S1 S[3:2] NC BA[N:0] A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 120 5% CK0 CK1 CK1 PAR_IN RESET
1:2 R E G I S T E R / P L L
RS0A CS0: SDRAMs D[3:0], D8 RS0B CS0: SDRAMs D[7:4] RS1A CS1: SDRAMs D[12:9], D17 RS1B CS1: SDRAMs D[16:13] RBA[N:0]A BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B A[N:0]: SDRAMs D[7:4], D[16:13] RRASA RAS: SDRAMs D[3:0], D[12:8], D17 RRASB RAS: SDRAMs D[7:4], D[16:13] RCASA CAS: SDRAMs D[3:0], D[12:8], D17 RCASB CAS: SDRAMs D[7:4], D[16:13] RWEA WE: SDRAMs D[3:0], D[12:8], D17 RWEB WE: SDRAMs D[7:4], D[16:13] RCKE0A CKE0: SDRAMs D[3:0], D8 RCKE0B CKE0: SDRAMs D[7:4] RCKE1A CKE1: SDRAMs D[12:9], D17 RCKE1B CKE1: SDRAMs D[16:13] RODT0A ODT0: SDRAMs D[3:0], D8 RODT0B ODT0: SDRAMs D[7:4] RODT1A ODT1: SDRAMs D[12:9], D17 RODT1A ODT1: SDRAMs D[16:13] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] PCK1A CK: SDRAMs D[12:9], D17 PCK1B CK: SDRAMs D[16:13] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] PCK1A CK: SDRAMs D[12:9], D17 PCK1B CK: SDRAMs D[16:13]
120 5%
OERR Err_Out RST RST: SDRAMs D[17:0]
* S[3:2], CK1 and CK1 are NC
Rev. 0.2 / Feb. 2010
14
4GB, 512Mx72 Module(1Rank of x4) - page1
A[O:N]A /BA[O:N]A
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
D8
ODT CAS CK CKE WE CK
D17
ODT CK CKE WE CK
D4
ODT CAS CK CKE WE CK
D13
ODT ODT ODT ODT CAS CK CKE WE CK
A[O:N]/BA[O:N]
ZQ
VSS
VSS
VSS
RAS
RAS
RAS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
D3
ODT CAS CK CKE WE CK
D12
ODT CAS CK CKE WE CK
D5
ODT CK CKE WE CK
D14
CK CKE WE CK
A[O:N]/BA[O:N]
ZQ
VSS
VSS
VSS
RAS
RAS
RAS
RAS
CAS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
D2
ODT CK CKE CAS WE CK
D11
ODT CK CKE CAS WE CK
D6
ODT CK CKE WE CK
D15
CK CKE WE CK
A[O:N]/BA[O:N]
ZQ
VSS
VSS
VSS
RAS
RAS
RAS
RAS
CAS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
D1
ODT CAS CK CKE WE CK
D10
ODT CAS CK CKE WE CK
D7
ODT CK CKE WE CK
D16
CK CKE WE CK
A[O:N]/BA[O:N]
VSS
VSS
VSS
RAS
RAS
RAS
RAS
CAS
A[O:N]/BA[O:N]
D0
ODT CAS CK CKE WE CK
D9
ODT CAS CK CKE WE CK
A[O:N]/BA[O:N]
VSS
RAS
Vtt
VDDSPD EVENT SCL SDA
VDDSPD
RAS
CS
CS
SA0
SA0 SA1 SA2 VSS
VSS
DQS0 DQS0 VSS DQ[3:0]
DQS DQS DM DQ [3:0]
ZQ
DQS9 DQS9 VSS DQ[7:4]
DQS DQS DM DQ [3:0]
ZQ
Vtt
EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
VDDSPD VDD VTT VREFCA VREFDQ VSS SPD
D0-D17 D0-D17 D0-D17 D0-D17 D0-D17
Note:
1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 15%. 5 3. See the wiring diagrams for all resistors associated with the command, address and control bus. 1 4. ZQ resistors are 240%. For all other resistor values refer to the appropriate wiring diagram.
Rev. 0.2 / Feb. 2010
CAS
CS
CS
CS
CS
VSS
DQS1 DQS1 VSS DQ[11;8]
DQS DQS DM DQ [3:0]
ZQ
DQS10 DQS10 VSS DQ[15:12]
DQS DQS DM DQ [3:0]
ZQ
DQS7 DQS7 VSS DQ[59:56]
DQS DQS DM DQ [3:0]
ZQ
DQS16 DQS16 VSS DQ[63:60]
DQS DQS DM DQ [3:0]
CAS
CS
CS
CS
CS
VSS
DQS2 DQS2 VSS DQ[19:16]
DQS DQS DM DQ [3:0]
ZQ
DQS11 DQS11 VSS DQ23:20]
DQS DQS DM DQ [3:0]
ZQ
DQS6 DQS6 VSS DQ[51:48]
DQS DQS DM DQ [3:0]
ZQ
DQS15 DQS15 VSS DQ[55;52]
DQS DQS DM DQ [3:0]
CAS
CS
CS
CS
CS
VSS
DQS3 DQS3 VSS DQ[27:24]
DQS DQS DM DQ [3:0]
ZQ
DQS12 DQS12 VSS DQ[31:28]
DQS DQS DM DQ [3:0]
ZQ
DQS5 DQS5 VSS DQ[43:40]
DQS DQS DM DQ [3:0]
ZQ
DQS14 DQS14 VSS DQ[47:44]
DQS DQS DM DQ [3:0]
RAS
CAS
CS
CS
CS
CS
VSS
DQS8 DQS8 VSS CB[3:0]
DQS DQS DM DQ [3:0]
ZQ
DQS17 DQS17 VSS CB[7:4]
DQS DQS DM DQ [3:0]
ZQ
DQS4 DQS4 VSS DQ[35:32]
DQS DQS DM DQ [3:0]
ZQ
A[O:N]B /BA[O:N]B
RODT0A
RS0A RRASA
RS0B RRASB
RODT0B
PCK0A RCKE0A
PCK0B RCKE0B
RCASA
RCASB
PCK0A
PCK0B
RWEA
RWEB
DQS13 DQS13 VSS DQ[39:36]
DQS DQS DM DQ [3:0]
ZQ
15
4GB, 512Mx72 Module(1Rank of x4) - page2
S0 S1 BA[N:0] A[N:0] RAS CAS WE CKE0 ODT0 CK0 RS0A CS0: SDRAMs D[3:0], D[12:8], D17 RS0B CS0: SDRAMs D[7:4], D[16:13] RS1A CS1: SDRAMs D[12:9], D17 RS1B CS1: SDRAMs D[16:13] RBA[N:0]A BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B A[N:0]: SDRAMs D[7:4], D[16:13] RRASA RAS: SDRAMs D[3:0], D[12:8], D17 RRASB RAS: SDRAMs D[7:4], D[16:13] RCASA CAS: SDRAMs D[3:0], D[12:8], D17 RCASB CAS: SDRAMs D[7:4], D[16:13] RWEA WE: SDRAMs D[3:0], D[12:8], D17 RWEB WE: SDRAMs D[7:4], D[16:13] RCKE0A CKE0: SDRAMs D[3:0], D[12:8], D17 RCKE0B CKE0: SDRAMs D[7:4], D[16:13] RODT0A ODT0: SDRAMs D[3:0], D[12:8]. D17 RODT0B ODT0: SDRAMs D[7:4], D[16:13] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] OERR Err_Out RESET RST RST: SDRAMs D[17:0]
1:2 R E
G
I S T E R / P L L
CK0 PAR_IN
* S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused register inputs ODT1 and CKE1 have a 330 resistor to ground.)
Rev. 0.2 / Feb. 2010
16
DQS0 DQS0 DM0/TDQS9 TDQS9 DQ[7:0]
DQS8 DQS8 DM8/TDQS17 TDQS17 CB[7:0]
DQS3 DQS3 DM3/TDQS12 TDQS12 DQ[31:24]
DQS2 DQS2 DM2/TDQS11 TDQS11 DQ[32:16]
DQS1 DQS1 DM1/TDQS10 TDQS10 DQ[15:8]
Vtt
CS CS CS CS CS
CS0 WRAS WCAS WWE PCK0 PCK0 WCKE0 WODT0 WA[N:0] WBA[N:0]
DQS DQS TDQS TDQS DQ [7:0] ZQ
RAS CAS WE CK CK CK CK CK WE WE WE WE CAS CAS CAS CAS RAS RAS RAS RAS
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
Rev. 0.2 / Feb. 2010
8GB, 1Gx72 Module(4Rank of x8) - page1
U6
CK CKE ODT A[N:O] BA[N:O] BA[N:O] BA[N:O] BA[N:O] BA[N:O] A[N:O] A[N:O] A[N:O] A[N:O] ODT ODT ODT ODT CKE CKE CKE CKE CK CK CK CK CS RAS CAS WE CK CK CK CK WE WE WE CAS CAS CAS RAS RAS RAS CS CS CS CS RAS CAS WE CK
U5
U4
U3
U2
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
CS1
PCK0
U15
CK CKE ODT A[N:O] BA[N:O] BA[N:O] BA[N:O] A[N:O] A[N:O] A[N:O] BA[N:O] ODT ODT ODT CKE CKE CKE CK CK CK CS RAS CAS WE CK CK CK WE WE CAS CAS RAS RAS CS CS CS RAS CAS WE CK
U14
U13
U12
U11
CK CKE ODT A[N:O] BA[N:O]
PCK0 WCKE01 VDD
CS RAS CAS WE CK
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
CS2
PCK2
U24
CK CKE ODT A[N:O] BA[N:O] BA[N:O] A[N:O] ODT CKE CKE ODT A[N:O] BA[N:O] CK CK CS RAS CAS WE CK CK WE CAS RAS CS CS RAS CAS WE CK
U23
U22
U21
U20
CK CKE ODT A[N:O] BA[N:O]
CK CKE ODT A[N:O] BA[N:O]
PCK2 WCKE0 WODT1
CS RAS CAS WE CK
CS RAS CAS WE CK
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
DQS DQS TDQS TDQS DQ [7:0] ZQ
CS3
PCK2
U33
CK CKE ODT A[N:O] BA[N:O]
U32
U31
U30
U29
CK CKE ODT A[N:O] BA[N:O]
CK CKE ODT A[N:O] BA[N:O]
CK CKE ODT A[N:O] BA[N:O]
CK CKE ODT A[N:O] BA[N:O]
PCK2 WCKE1 VDD
17
8GB, 1Gx72 Module(4Rank of x8) - page2
WBA[N:0] WA[N:0] WODT0 WCKE01 WODT1 WCKE0 WCKE0 WCKE1
CKE
WRAS
WCAS
WWE
PCK0
PCK0
PCK2
PCK0
PCK0
PCK2
PCK2
VDD
PCK2
CK
CS0
CS1
CS2
CK
CK
CK
CK
CK
CK
CS3
CKE
CKE
CKE
WE
WE
WE
ODT
ODT
ODT
WE
CK
A[N:O]
A[N:O]
A[N:O]
ODT ODT ODT ODT
CAS
CAS
CAS
RAS
RAS
RAS
RAS
CAS
CS
CS
CS
CS
VDD
A[N:O] A[N:O] A[N:O] A[N:O] BA[N:O] BA[N:O] BA[N:O] BA[N:O]
BA[N:O]
BA[N:O]
DQS4 DQS4 DM4/TDQS13 TDQS13 DQ[39:32]
DQS DQS TDQS TDQS DQ [7:0] ZQ
U7
DQS DQS TDQS TDQS DQ [7:0] ZQ
U16
DQS DQS TDQS TDQS DQ [7:0] ZQ
BA[N:O]
U25
DQS DQS TDQS TDQS DQ [7:0] ZQ
U34
CK
CK
CK
CK
CK
CK
CK CK CK
CKE
CKE
CKE
CK CK CK
ODT
ODT
ODT
RAS
RAS
RAS
A[N:O]
A[N:O]
BA[N:O]
BA[N:O]
A[N:O]
DQS5 DQS5 DM5/TDQS14 TDQS14 DQ[47:40]
DQS DQS TDQS TDQS DQ [7:0] ZQ
U8
DQS DQS TDQS TDQS DQ [7:0] ZQ
U17
DQS DQS TDQS TDQS DQ [7:0] ZQ
BA[N:O]
U26
DQS DQS TDQS TDQS DQ [7:0] ZQ
RAS
U35
CAS
CAS
CAS
RAS
RAS
RAS
A[N:O]
A[N:O]
A[N:O]
RAS
CAS
CS
CS
CS
CK
CK
CK
CK
CK
CKE
CKE
CK
CKE
CS
ODT
ODT
BA[N:O]
BA[N:O]
ODT
DQS6 DQS6 DM6/TDQS15 TDQS15 DQ[55:48]
DQS DQS TDQS TDQS DQ [7:0] ZQ
U9
DQS DQS TDQS TDQS DQ [7:0] ZQ
U18
DQS DQS TDQS TDQS DQ [7:0] ZQ
BA[N:O]
U27
DQS DQS TDQS TDQS DQ [7:0] ZQ
U36
CAS
CAS
CAS
RAS
RAS
RAS
A[N:O]
A[N:O]
A[N:O]
RAS
CAS
CS
CS
CS
CK
CK
CK
CK
CK
CKE
CKE
CK
CKE
CS
ODT
ODT
BA[N:O]
BA[N:O]
ODT
DQS3 DQS3 DM3/TDQS12 TDQS12 DQ[31:24]
DQS DQS TDQS TDQS DQ [7:0] ZQ
U10
DQS DQS TDQS TDQS DQ [7:0] ZQ
U19
DQS DQS TDQS TDQS DQ [7:0] ZQ
BA[N:O]
U28
DQS DQS TDQS TDQS DQ [7:0] ZQ
U37
Vtt
VDDSPD EVENT SCL SDA
VDDSPD
SA0
SA0 SA1 SA2 VSS
EVENT SPD with SA1 Integrated SA2 SCL TS SDA VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
VDDSPD
CKE
WE
WE
WE
WE
CKE
WE
WE
WE
WE
CKE
WE
WE
WE
CAS
CAS
CAS
CAS
WE
CS
CS
CS
CS
Serial PD
U1-U37
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. See wiring diagrams for resistor values. 3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
VDD VTT VREFCA VREFDQ VSS
U1-U37 U1-U37 U1-U37
Rev. 0.2 / Feb. 2010
18
8GB, 1Gx72 Module(4Rank of x8) - page3
S0 S1 S2 S3 BA[N:0] A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0
1:2 R E G I S T E R / P L L
CK0 CK1 CK1 PAR_IN RESET RST
120 5%
CS0 CS0: SDRAMs U[10:2] CS1 CS1: SDRAMs U[19:11] CS2 CS2: SDRAMs U[28:20] CS3 CS3: SDRAMs U[37:29] WBA[N:0] BA[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EBA[N:0] BA[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WA[N:0] A[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EA[N:0] A[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WRAS RAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] ERAS RAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WCAS CAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] ECAS CAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WWE WE: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EWE WE: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WCKE0 CKE0: SDRAMs U[6:2], U[24:20] ECKE0 CKE0: SDRAMs U[10:7], U[28:25] WCKE1 CKE1: SDRAMs U[15:11], U[33:29] ECKE1 CKE1: SDRAMs U[19:16], U[37:34] WODT0 ODT0: SDRAMs U[6:2] EODT0 ODT0: SDRAMs U[10:7] WODT0 ODT1: SDRAMs U[24:20] EODT0 ODT1: SDRAMs U[28:25] PCK0 CK: SDRAMs U[6:2], U[15:11] PCK1 CK: SDRAMs U[10:7], U[28:25] PCK2 CK: SDRAMs U[24:20], U[33:29] PCK3 CK: SDRAMs U[19:16], U[37:34] PCK0 CK: SDRAMs U[6:2], U[15:11] PCK1 CK: SDRAMs U[10:7], U[28:25] PCK2 CK: SDRAMs U[24:20], U[33:29] PCK3 CK: SDRAMs U[19:16], U[37:34] Err_Out RST: SDRAMs U[37:2]
Rev. 0.2 / Feb. 2010
19
DQS10 DQS10 VSS DQ[15:12]
DQS11 DQS11 VSS DQ[23:20]
DQS12 DQS12 VSS DQ[31:28]
DQS17 DQS17 VSS CB[7:4]
DQS0 DQS0 VSS DQ[3:0]
Vtt
CS CS RAS CAS RAS CAS CAS CAS CAS RAS RAS RAS
DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0]
CS
CS
CS
RS0A RRASA RCASA RWEA PCK0A PCK0A RCKE0A RODT0A A[O:N]A /BA[O:N]A
WE WE
WE
WE
WE
D0
CK CK CK CKE ODT A[N:O]/BA[N:O] CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK
Rev. 0.2 / Feb. 2010
D10 D11 D12 D17
CK CK CKE ODT A[N:O]/BA[N:O] CS RAS CAS WE WE WE WE CAS CAS CAS RAS RAS RAS CS CS CS CS RAS CAS WE
DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0]
RS1A
D18
CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT A[N:O]/BA[N:O] CK CKE CK CKE CK CK
D28
D29
D30
D35
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT
PCK1A PCK1A RCKE1A R0DT1A
A[N:O]/BA[N:O]
DQS2 DQS2 VSS DQ[19:16]
DQS3 DQS3 VSS DQ[27:24]
DQS8 DQS8 VSS CB[3:0]
8GB, 1Gx72 Module(2Rank of x4) - page1
DQS1 DQS1 VSS DQ[11:8]
DQS9 DQS9 VSS DQ[7:4]
Vtt
CS RAS CAS WE WE WE CAS CAS CK CK CKE ODT A[N:O]/BA[N:O] RAS RAS CS CS
DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0]
CS RAS CAS WE
CS RAS CAS WE
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RS0A RRASA RCASA RWEA
D9
CK CK CKE ODT A[N:O]/BA[N:O] CS RAS CAS WE CK CK CKE ODT A[N:O]/BA[N:O]
DQS DQS DM DQ [3:0] DQS DQS DM DQ [3:0]
D1
D2
D3
D8
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT
CK CK CKE ODT A[N:O]/BA[N:O]
PCK0A PCK0A RCKE0A RODT0A
A[N:O]/BA[N:O]
A[O:N]A /BA[O:N]A
CS RAS CAS WE
CS RAS CAS WE
CS RAS CAS WE
CS RAS CAS WE
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RS1A
D27
D19
D20
D21
D26
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
PCK1A PCK1A RCKE1A R0DT1A
A[N:O]/BA[N:O]
20
8GB, 1Gx72 Module(2Rank of x4) - page2
A[N:O]B /BA[N:O]B RODT0B A[N:O]B /BA[N:O]B RODT0B
PCK0B RCKE0B
PCK0B RCKE0B
R0DT1B
RCKE1B
RS0B RRASB
RS0B RRASB
RCASB
PCK1B
PCK1B
PCK1B
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D14
ODT CAS CK CKE WE CK
D32
ODT CK CKE WE CK
D13
ODT CAS CK CKE WE CK
D31
ODT ODT ODT ODT CAS CK CKE CK CKE CK CKE CK CKE WE CK
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D4
ODT CAS CK CKE WE CK
D22
ODT CAS CK CKE WE CK
D5
ODT CK CKE WE CK
D23
WE CK
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D16
ODT CK CKE CAS WE CK
D34
ODT CK CKE CAS WE CK
D15
ODT CK CKE WE CK
D33
WE CK
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D7
ODT CAS CK CKE WE CK
D25
ODT CAS CK CKE WE CK
D6
ODT CK CKE WE CK
D24
WE CK
Vtt
Vtt
VDDSPD VDD VTT VREFCA VREFDQ VSS
SPD
D0-D35 D0-D35 D0-D35 D0-D35 D0-D35
VDDSPD EVENT SCL SDA
VDDSPD
SA0
SA0 SA1 SA2 VSS
EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble. 2. See wiring diagrams for all resistors values. 3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
Rev. 0.2 / Feb. 2010
A[N:O]/BA[N:O]
DQS7 DQS7 VSS DQ[59:56]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS6 DQS6 VSS DQ[51:48]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RAS
RAS
RAS
RAS
CAS
CAS
CS
CS
CS
CS
A[N:O]/BA[N:O]
DQS16 DQS16 VSS DQ[63:60]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS15 DQS15 VSS DQ[55:52]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RAS
RAS
RAS
RAS
CAS
CAS
CS
CS
CS
CS
A[N:O]/BA[N:O]
DQS4 DQS4 VSS DQ[35:32]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
DQS5 DQS5 VSS DQ[43:40]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RAS
RAS
RAS
RAS
CAS
CAS
CS
CS
CS
CS
A[N:O]/BA[N:O]
DQS14 DQS14 VSS DQ[47:44]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RS1B
DQS13 DQS13 VSS DQ[39:36]
DQS DQS DM DQ [3:0]
DQS DQS DM DQ [3:0]
RAS
RAS
RAS
RAS
CAS
CS
CS
CS
CS
PCK1B
RS1B
R0DT1B
RCKE1B
RCASB
PCK0B
RWEB
PCK0B
RWEB
21
8GB, 1Gx72 Module(2Rank of x4) - page3
S0 S1 BA[N:0] A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0
1:2 R E G I S T E R / P L L
RS0A CS0: SDRAMs D[3:0], D[12:8], D17 RS0B CS0: SDRAMs D[7:4], D[16:13] RS1A CS1: SDRAMs D[21:18], D[30:26], D35 RS1B CS1: SDRAMs D[25:22], D[34:31] RBA[N:0]A BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RBA[N:0]B BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RA[N:0]A A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RA[N:0]B A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RRASA RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RRASB RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCASA CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RCASB CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RWEA WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RWEB WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCKE0A CKE0: SDRAMs D[3:0], D[12:8], D17 RCKE0B CKE0: SDRAMs D[7:4], D[16:13] RCKE1A CKE1: SDRAMs D[21:18], D[30:26], D35 RCKE1B CKE1: SDRAMs D[25:22], D[34:31] RODT0A ODT0: SDRAMs D[3:0], D[12:8], D17 RODT0B ODT0: SDRAMs D[7:4], D[16:13] RODT1A ODT1: SDRAMs D[21:18], D[30:26], D35 RODT1A ODT1: SDRAMs D[25:22], D[34:31] PCK0A CK: SDRAMs D[3:0], D[12:8], D17 PCK0B CK: SDRAMs D[7:4], D[16:13] PCK1A CK: SDRAMs D[21:18], D[30:26], D35 PCK1B CK: SDRAMs D[25:22], D[34:31] PCK0A CK: SDRAMs D[3:0], D[12:8], D17 PCK0B CK: SDRAMs D[7:4], D[16:13] PCK1A CK: SDRAMs D[21:18], D[30:26], D35 PCK1B CK: SDRAMs D[25:22], D[34:31]
CK0 CK1 CK1 PAR_IN RESET RST
120 5%
Err_Out RST: SDRAMs D[35:0]
* S[3:2], CK1 and CK1 are NC
Rev. 0.2 / Feb. 2010
22
VSS DQS8 DQS8 VSS CB[3:0]
VSS DQS0 DQS0 VSS DQ[3:0]
VSS DQS1 DQS1 VSS DQ[11:8]
VSS DQS2 DQS2 VSS DQ[19:16]
VSS DQS3 DQS3 VSS DQ[27:24]
Vtt
CS CS RAS CAS WE RAS CAS WE CAS WE CAS WE CAS WE RAS RAS RAS
ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0]
CS
CS
CS
ARS0A ARRASA ARCASA ARWEA APCK0A APCK0A ARCKE0A ARODT0A ARA[N:O]A /ARBA[N:O]A
Rev. 0.2 / Feb. 2010
D1 D9
CK CK CK CKE ODT A[N:O]/BA[N:O] CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK
VSS VSS VSS VSS VSS
D3
D5
D7
CK CK CKE ODT A[N:O]/BA[N:O]
CS RAS CAS WE WE WE WE CAS CAS CAS RAS RAS RAS
CS
CS
CS
CS RAS CAS WE CK CK CKE ODT
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ARS1A
D0
CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT A[N:O]/BA[N:O] CK CKE CK CKE CK CK
VSS VSS VSS
D2
D4
D6
D8
CK CK CKE ODT A[N:O]/BA[N:O]
ARCKE1A VDD
A[N:O]/BA[N:O]
VSS
16GB, 2Gx72 Module(4Rank of x4) - page1
VSS
CS RAS CAS WE WE WE CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT CK CKE CK CK CK CKE ODT A[N:O]/BA[N:O] CAS CAS RAS RAS
CS
CS
CS RAS CAS WE CK CK CKE ODT
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS2A BRRASA BRCASA BRWEA
D53
VSS VSS
D51
D49
VSS
A[N:O]/BA[N:O]
D47
VSS
D45
CK CK CKE ODT A[N:O]/BA[N:O]
VSS
BPCK0A BPCK0A BRCKE0A BRODT1A BRA[N:O]A /BRBA[N:O]A
CS RAS CAS WE
CS RAS CAS WE CK CK CKE ODT
CS RAS CAS WE
CS RAS CAS WE
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS3A
D52
D50
D48
D46
D44
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
BRCKE1A VDD
A[N:O]/BA[N:O]
23
VSS DQS17 DQS17 VSS CB[7:4]
VSS DQS9 DQS9 VSS DQ[7:4]
VSS DQS10 DQS10 VSS DQ[11:8]
VSS DQS11 DQS11 VSS DQ[23:20]
VSS DQS12 DQS12 VSS DQ[31:28]
Vtt
CS CS RAS CAS WE RAS CAS WE CAS WE CAS WE CAS WE RAS RAS RAS
ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0]
CS
CS
CS
ARS0A ARRASA ARCASA ARWEA APCK0A APCK0A ARCKE0A ARODT0A ARA[N:O]A /ARBA[N:O]A
Rev. 0.2 / Feb. 2010
D19 D27
CK CK CK CKE ODT A[N:O]/BA[N:O] CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE CK CKE CK CK
VSS VSS VSS VSS VSS
D21
D23
D25
CK CK CKE ODT A[N:O]/BA[N:O]
CS RAS CAS WE WE WE WE CAS CAS CAS RAS RAS RAS
CS
CS
CS
CS RAS CAS WE CK CK CKE ODT
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ARS1A
D18
CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT A[N:O]/BA[N:O] CK CKE CK CKE CK CK
VSS VSS VSS
D20
D22
D24
D26
CK CK CKE ODT A[N:O]/BA[N:O]
ARCKE1A VDD
A[N:O]/BA[N:O]
VSS
16GB, 2Gx72 Module(4Rank of x4) - page2
VSS
CS RAS CAS WE WE WE CK CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT CK CKE CK CK CK CKE ODT A[N:O]/BA[N:O] CAS CAS RAS RAS
CS
CS
CS RAS CAS WE CK CK CKE ODT
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS2A BRRASA BRCASA BRWEA
D71
VSS VSS
D69
D67
VSS
A[N:O]/BA[N:O]
D65
VSS
D63
CK CK CKE ODT A[N:O]/BA[N:O]
VSS
BPCK0A BPCK0A BRCKE0A BRODT1A BRA[N:O]A /BRBA[N:O]A
CS RAS CAS WE
CS RAS CAS WE CK CK CKE ODT
CS RAS CAS WE
CS RAS CAS WE
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS3A
D70
D68
D66
D64
D62
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
CK CK CKE ODT A[N:O]/BA[N:O]
BRCKE1A VDD
A[N:O]/BA[N:O]
24
VSS DQS7 DQS7 VSS DQ[59:56
VSS DQS6 DQS6 VSS DQ[51:48]
VSS DQS5 DQS5 VSS DQ[43:40]
VSS DQS4 DQS4 VSS DQ[35:32]
Vtt
CS CS RAS CAS WE RAS CAS WE CAS WE CAS WE RAS RAS
ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0]
CS
CS
ARS0B ARRASB ARCASB ARWEB APCK0B APCK0B ARCKE0B ARODT0B ARA[N:O]B /ARBA[N:O]B
Rev. 0.2 / Feb. 2010
D17 D11
CK CK CK CKE ODT A[N:O]/BA[N:O] CK CKE ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT CK CKE CK
VSS VSS VSS VSS
D15
D13
CK CK CKE ODT A[N:O]/BA[N:O]
CS RAS CAS WE WE WE CAS CAS RAS RAS
CS
CS
CS RAS CAS WE CK CK CKE ODT
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ARS1B
D16
CK CK CKE ODT A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] CK CKE CK
VSS VSS
D14
D12
D10
CK CK CKE ODT A[N:O]/BA[N:O]
ARCKE1B VDD
A[N:O]/BA[N:O]
VSS
16GB, 2Gx72 Module(4Rank of x4) - page3
VSS
CS RAS CAS WE WE CK CK CKE ODT A[N:O]/BA[N:O] CK CK CKE ODT A[N:O]/BA[N:O] CAS RAS
CS
CS RAS CAS WE CK CK CKE ODT
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS2B BRRASB BRCASB BRWEB
D37
VSS ZQ DQS DQS DM DQ [3:0]
D39
VSS
A[N:O]/BA[N:O]
D41
VSS
D13
CK CK CKE ODT A[N:O]/BA[N:O]
VSS
BPCK0B BPCK0B BRCKE0B BRODT1B BRA[N:O]B /BRBA[N:O]B
CS RAS CAS WE CK CK CKE ODT
CS RAS CAS WE
CS RAS CAS WE
CS RAS CAS WE
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
ZQ DQS DQS DM DQ [3:0]
BRS3B
A[N:O]/BA[N:O]
D36
D38
CK CK CKE ODT A[N:O]/BA[N:O]
D40
CK CK CKE ODT A[N:O]/BA[N:O]
D42
CK CK CKE ODT A[N:O]/BA[N:O]
BRCKE1B VDD
25
16GB, 2Gx72 Module(4Rank of x4) - page4
ARA[N:O]B /ARBA[N:O]B BRA[N:O]B /BRBA[N:O]B
ARODT0B
ARCKE1B
BRODT1B
APCK0B ARCKE0B
BPCK0B BRCKE0B
BRCKE1B
ARS0B ARRASB
ARCASB
BRS2B BRRASB
BRCASB
APCK0B
ARS1B
BPCK0B
ARWEB
BRWEB
BRS3B
VDD
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D29
ODT CAS WE CK CKE CK
D28
ODT CK CKE WE CK
D61
ODT CK CKE WE CK
D60
ODT ODT ODT ODT CK CKE CK CKE CK CKE CK CKE WE CK
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D31
ODT CK CKE CK
D30
ODT CK CKE WE CK
D59
ODT CK CKE WE CK
D58
WE CK
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D33
ODT CK CKE CK
D32
ODT CK CKE WE CK
D57
ODT CK CKE WE CK
D56
WE CK
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D35
ODT CK CKE CK
D34
ODT CK CKE WE CK
D55
ODT CK CKE WE CK
D54
WE CK
Vtt
VDDSPD VDD VTT VREFCA VREFDQ VSS
SPD
D0-D71
VDDSPD EVENT SCL SDA
VDDSPD
SA0
SA0 SA1 SA2 VSS
D0-D71 D0-D71 D0-D71
EVENT SPD with SA1 Integrated SA2 SCL TS SDA VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer's requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 15 Ohms 5%. 3. See the wiring diagrams for all resistors associated with the command, address and control bus. 4. ZQ resistors are 240 Ohms 1%. For all other resistor values refer to the appropriate wiring diagram.
Rev. 0.2 / Feb. 2010
A[N:O]/BA[N:O]
VSS DQS16 DQS16 VSS DQ[63:60]
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
RAS
RAS
RAS
RAS
CAS WE
CAS
CAS
CAS
CS
CS
CS
CS
A[N:O]/BA[N:O]
VSS DQS15 DQS15 VSS DQ[55:52]
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
RAS
RAS
RAS
RAS
CAS WE
CAS
CAS
CAS
CS
CS
CS
CS
A[N:O]/BA[N:O]
VSS DQS14 DQS14 VSS DQ[47:44]
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
RAS
RAS
RAS
RAS
CAS WE
CAS
CAS
CAS
CS
CS
CS
CS
A[N:O]/BA[N:O]
VSS DQS13 DQS13 VSS DQ[39:36]
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
VSS
ZQ DQS DQS DM DQ [3:0]
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CS
CS
CS
CS
VDD
26
16GB, 2Gx72 Module(4Rank of x4) - page5
S0
1:2 R E G I S T E R / P L L A
ARS0A CS1: SDRAMs D1,D3,D5,D7 D9, D19, D21, D23, D25, D27 ARS0B CS1: SDRAMs D11, D13, D15, D17, D29, D31, D33, D35
S2
1:2 R E G I S T E R / P L L B
BRS2A CS1: SDRAMs D45,D47,D49,D51,D53 D63,D65,D67,D69,D71 BRS2B CS1: SDRAMs D37,D39,D41,D43, D55,D57,D59,D61 BRS3A CS0: SDRAMs D44.D46,D48,D50,D52, D62,D64,D66,D68,D70 BRS3B CS0: SDRAMs D36,D38,D40,D42, D54,D56,D58,D60 BRBA[N:0]A BA[N:0]: SDRAMs D[53:44],D[71:62] BRBA[N:0]B BA[N:0]: SDRAMs D[43:36],D[61:54] BRA[N:0]A A[N:0]: SDRAMs D[55:44],D[71:62] BRA[N:0]B A[N:0]: SDRAMs D[43:36],D[61:54] BRRASA RAS: SDRAMs D[53:44],D[71:62] BRRASB RAS: SDRAMs D[43:36],D[61:54] BRCASA CAS: SDRAMs D[53:44],D[71:62] BRCASB CAS: SDRAMs D[43:36],D[61:54] BRWEA WE: SDRAMs D[53:44],D[71:62] BRWEB WE: SDRAMs D[43:36],D[61:54] BRCKE0A CKE1: SDRAMs D45,D47,D49,D51,D53, D63,D65,D67,D69,D71 BRCKE0B CKE1: SDRAMs D37,D39,D41,D43, D55,D57,D59,D61 BRCKE1A CKE0: SDRAMs D44.D46,D48,D50,D52, D62,D64,D66,D68,D70 BRCKE1B CKE0: SDRAMs D36,D38,D40,D42, D54,D56,D58,D60 BRODT1A ODT1: SDRAMs D45,D47,D49,D51,D53 D63,D65,D67,D69,D71 BRODT1B ODT0: SDRAMs D37,D39,D41,D43 D55,D57,D59,D61 BPCK0A CK: SDRAMs D[53:44] BPCK0B CK: SDRAMs D[43:36] BPCK1A CK: SDRAMs D[71:62] BPCK1B CK: SDRAMs D[61:54] BPCK0A CK: SDRAMs D[53:44] BPCK0B CK: SDRAMs D[43:36] BPCK1A CK: SDRAMs D[71:62] BPCK1B CK: SDRAMs D[61:54] Err_Out
S1
BA[N:0] A[N:0] RAS CAS WE CKE0
CKE1
ODT0
CK0
120 5%
CK0
ARS1A CS0: SDRAMs D0, D2, D4, D6, D8, D18, D20, D22, D24, D26 ARS1B CS0: SDRAMs D10, D12, D14, D16, D28, D30, D32, D34 ARBA[N:0]A BA[N:0]: SDRAMs D[9:0],D[27:18] BA[N:0] ARBA[N:0]B BA[N:0]: SDRAMs D[17:10],D[35:28] ARA[N:0]A A[N:0]: SDRAMs D[9:0],D[27:18] A[N:0] ARA[N:0]B A[N:0]: SDRAMs D[17:10],D[35:28] RAS ARRASA RAS: SDRAMs D[9:0],D[27:18] ARRASB RAS: SDRAMs D[17:10],D[35:28] ARCASA CAS: SDRAMs D[9:0],D[27:18] CAS ARCASB CAS: SDRAMs D[17:10],D[35:28] ARWEA WE: SDRAMs D[9:0],D[27:18] WE ARWEB WE: SDRAMs D[17:10],D[35:28] ARCKE0A CKE1: SDRAMs D1,D3,D5,D7,D9, CKE0 D19, D21, D23, D25, D27 ARCKE0B CKE1: SDRAMs D11,D13,D15,D17, D29, D31, D33, D35 CKE1 ARCKE1A CKE0: SDRAMs D0,D2,D4,D6,D8, D18, D20, D22, D24, D26 ARCKE1B CKE0: SDRAMs D10,D12,D14,D16, D28, D30, D32, D34 ARODT0A ODT1: SDRAMs D1,D3,D5,D7,D9, ODT1 D19, D21, D23, D25, D27 ARODT0B ODT0: SDRAMs D11,D13,D15,D17, D29, D31, D33, D35 APCK0A CK: SDRAMs D[9:0] CK0 APCK0B CK: SDRAMs D[17:10] 120 APCK1A CK: SDRAMs D[27:18] 5% APCK1B CK: SDRAMs D[35:28] APCK0A CK: SDRAMs D[9:0] CK0 APCK0B CK: SDRAMs D[17:10] APCK1A CK: SDRAMs D[27:18] APCK1B CK: SDRAMs D[35:28] Err_Out PAR_IN RESET RST: SDRAMs D[35:0]
S3
PAR_IN RESET RST
RST
CK1 CK1
120 5%
1. CK0 and CK0 are differentially terminated with a single 120 Ohms 5% resistor. 2. CK1 and CK1 are differentially terminated with a single 120 Ohms 5% resistor, but is not used.
3. Unused register inputs ODT1 for Register A and ODT0 for Register B are tied to ground. 4. The module drawing on this page is not drawn to scale.
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Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol VDD VDDQ Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Rating - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V -55 to +100 Units V V V
o
Notes 1, 1, 1 1, 2
VIN, VOUT Voltage on any pin relative to Vss TSTG Notes: Storage Temperature
C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol TOPER Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Hynix DDR3 SDRAMs support Auto Self-Refresh and in Extended Temperature Range and please refer to Hynix component datasheet and/or the DIMM SPD for tREFI requirements in the Extended Temperature Range Parameter Normal Operating Temperature Range Extended Temperature Range Rating 0 to 85 85 to 95 Units
oC oC
Notes 1,2 1,3
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AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Symbol VDD VDDQ Notes: 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a very long period of time (e.g., 1 sec). 2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 3. Under these supply voltages, the device operates to this DDR3L specification. 4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation (see Figure 0). Parameter Supply Voltage Supply Voltage for Output Rating Min. 1.283 1.283 Typ. 1.35 1.35 Max. 1.45 1.45 Units V V Notes 1,2,3,4 1,2,3,4
Recommended DC Operating Conditions - - DDR3 (1.5V) operation
Symbol VDD VDDQ Notes: 1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications. 2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as defined for this device. 3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation (see Figure 0). Parameter Supply Voltage Supply Voltage for Output Rating Min. 1.425 1.425 Typ. 1.5 1.5 Max. 1.575 1.575 Units V V Notes 1,2,3 1,2,3
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Ta CK,CK#
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
VDD, VDDQ (DDR3) VDD, VDDQ (DDR3L) Tmin = 10ns
Tmin = 10ns
tCKSRX
Tmin = 200us T = 500us
RESET#
CKE
Tmin = 10ns tDLLK tIS tXPR MRS tMRD MRS tMRD MRS tMRD MRS tMOD ZQCL tZQinit 1)
VALID
COMMAND
READ
1)
VALID
BA
READ tIS
MR2
MR3
MR1
MR0
VALID tIS
ODT
READ
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID
RTT
NOTE 1: From time point "Td" until "Tk" NOP or DES commands must be applied between MRS and ZQCL commands.
TIME BREAK
DON'T CARE
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
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AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals AC and DC Input Levels for Single-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and Address
DDR3L-800/1066/1333 Symbol VIH.CA(DC90) VIL.CA(DC90) VIH.CA(AC160) VIL.CA(AC160) VIH.CA(AC135) VIL.CA(AC135) VRefCA(DC) Parameter Min DC input logic high DC input logic low AC input logic high AC input logic low AC Input logic high AC input logic low Reference Voltage for ADD, CMD inputs Vref + 0.09 VSS Vref + 0.160 Note2 Vref + 0.135 Note2 0.49 * VDD Max VDD Vref - 0.09 Note2 Vref - 0.160 Note2 Vref - 0.135 0.51 * VDD V V V V V V V 1 1 1, 2 1, 2 1, 2 1, 2 3, 4 Unit Notes
Notes: 1. For input only pins except RESET, Vref = VrefCA (DC). 2. Refer to "Overshoot and Undershoot Specifications" on page 44. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV 5. There levels apply for 1.35 volt (see table above) operation only. If the device is operated at 1.5V (table "Single Ended AC and DC Input Levels for DQ and DM" on page 32), the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) apply. The 1.5V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) do not apply when the device is operated in the 1.35 voltage range.
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AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below. DDR3 SDRAM will also support corresponding tDS values (Table 41 on page 120 and Table 47on page 145 in "DDR3L Device Operation") as well as derating tables Table 44 on page 139 in "Device Operation" depending on Vih/Vil AC levels.
Single Ended AC and DC Input Levels for DQ and DM
DDR3L-800/1066 Symbol VIH.CA(DC90) VIL.CA(DC90) VIH.CA(AC160) VIL.CA(AC160) VIH.CA(AC135) VIL.CA(AC135) VRefDQ(DC) Parameter Min DC input logic high Vref + 0.09 DC input logic low VSS AC input logic high Vref + 0.160 AC input logic low Note2 AC Input logic high Vref + 0.135 AC input logic low Note2 Reference Voltage for DQ, 0.49 * VDD DM inputs Max VDD Vref - 0.09 Note2 Vref - 0.160 Note2 Vref - 0.135 0.51 * VDD Min Vref + 0.09 VSS Vref + 0.135 Note2 0.49 * VDD Max VDD Vref - 0.09 Note2 Vref - 0.135 0.51 * VDD V V V V V V V 1 1 1, 2 1, 2 1, 2 1, 2 3, 4 DDR3L-1333 Unit Notes
Notes: 1. Vref = VrefDQ (DC). 2. Refer to "Overshoot and Undershoot Specifications" on page 44. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV 4. For reference: approx. VDD/2 +/- 13.5 mV 5. There levels apply for 1.35 volt (table "Single Ended AC and DC Input Levels for Command and Address" on page 31) operation only. If the device is operated at 1.5V (table above), the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) apply. The 1.5V levels (VIH/ L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) do not apply when the device is operated in the 1.35 voltage range.
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Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 39. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD.
voltage
VDD
VRef ac-noise VRef(DC)
VRef(t) VRef(DC)max VDD/2 VRef(DC)min
VSS
time
Illustration of VRef(DC) tolerance and VRef ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on VRef. "VRef " shall be understood as VRef(DC), as defined in figure above. This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
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AC and DC Logic Input Levels for Differential Signals
Differential signal definition
tDVAC VIL.DIFF.AC.MIN Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)
VIL.DIFF.MIN
0 half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and "time above ac-level" tDVAC
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Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Differential AC and DC Input Levels
DDR3L-800, 1066, 1333 Symbol VIHdiff VILdiff VIHdiff (ac) VILdiff (ac) Notes: 1. Used to define a differential signal slew-rate. 2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL (ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 44. Parameter Min Differential input high Differential input logic low Differential input high ac Differential input low ac + 0.180 Note 3 2 x (VIH (ac) - Vref) Note 3 Max Note 3 - 0.180 Note 3 2 x (VIL (ac) - Vref) V V V V 1 1 2 2 Unit Notes
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0 tDVAC [ps] @ |VIH/Ldiff (ac)| = 350mV min 75 57 50 38 34 29 22 13 0 0 max tDVAC [ps] @ |VIH/Ldiff (ac)| = 300mV min 175 170 167 163 162 161 159 155 150 150 max -
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Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac) / VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ's might be different per speed-bin etc. E.g., if VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and CK.
VDD or VDDQ
VSEHmin VSEH
VDD/2 or VDDQ/2 CK or DQS VSELmax
VSS or VSSQ
VSEL time
Single-ended requirements for differential signals. Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
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Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
DDR3L-800, 1066, 1333, & 1600 Symbol VSEH VSEL Notes: 1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac) of DQs. 2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 44. Parameter Min Single-ended high level for strobes Single-ended high level for Ck, CK Single-ended low level for strobes Single-ended low level for CK, CK (VDD / 2) + 0.175 (VDD /2) + 0.175 Note 3 Note 3 Max Note 3 Note 3 (VDD / 2) = 0.175 (VDD / 2) = 0.175 V V V V 1,2 1,2 1,2 1,2 Unit Notes
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Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in table below. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS
VDD CK, DQS
VIX VDD/2 VIX VIX
CK, DQS VSS
Vix Definition
Cross point voltage for differential input signals (CK, DQS)
DDR3L-800, 1066, 1333 Symbol VIX VIX Parameter Min Differential Input Cross Point Voltage relative to VDD/2 for CK, CK Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS -150 -175 -150 Max 150 175 150 mV mV mV 1 Unit Notes
Notes: 1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK - CK is larger than 3 V/ns. 2. Refer to the table "Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU" on page 37 for VSEL and VSEH standard values.
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Slew Rate Definitions for Single-Ended Input Signals
See 7.5 "Address / Command Setup, Hold and Derating" on page 138 in "DDR3L Device Operation" for single-ended slew rate definitions for address and command signals. See 7.6 "Data Setup, Hold and Slew Rate Derating" on page 145 in "DDR3L Device Operation" for singleended slew rate definition for data signals.
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table and figure below.
Differential Input Slew Rate Definition
Measured Description Min
Max
Defined by
Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Notes:
VILdiffmax VIHdiffmin
VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Differential Input Voltage (i.e. DQS-DQS; CK-CK)
Delta TRdiff vIHdiffmin
0
vILdiffmax Delta TFdiff
Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
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AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Single-ended AC and DC Output Levels
Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level (for output SR) DDR3L-800, 1066, 1333 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ VTT - 0.1 x VDDQ Unit V V V V V 1 1 Notes
Notes: 1. The swing of 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ / 2.
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Differential AC and DC Output Levels
Symbol VOHdiff (AC) VOLdiff (AC) Parameter AC differential output high measurement level (for output SR) AC differential output low measurement level (for output SR) DDR3L-800, 1066, 1333 + 0.2 x VDDQ - 0.2 x VDDQ Unit V V Notes 1 1
Notes: 1. The swing of 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ/2 at each of the differential outputs.
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Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below.
Single-ended Output slew Rate Definition
Description Single-ended output slew rate for rising edge Single-ended output slew rate for falling edge Measured From VOL(AC) VOH(AC) To VOH(AC) VOL(AC) Defined by [VOH(AC)-VOL(AC)] / DeltaTRse [VOH(AC)-VOL(AC)] / DeltaTFse
Notes: 1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Delta TRse Single Ended Output Voltage(l.e.DQ)
vOH(AC)
V
vOl(AC)
Delta TFse
Single Ended Output Slew Rate Definition
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)
DDR3L-800 Parameter Single-ended Output Slew Rate Symbol SRQse Min 1.75 Max 51) DDR3L-1066 Min 1.75 Max 51) DDR3L-1333 Min 1.75 Max 51)
Units
V/ns
Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting Note 1): In two cases, a maximum slew rate of 6 V/ns applies for a single DQ signal within a byte lane. Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static(i.e they stay at either high or low). Case_2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
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Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure below.
Differential Output Slew Rate Definition
Measured Description From Differential output slew rate for rising edge Differential output slew rate for falling edge VOLdiff (AC) VOHdiff (AC) To VOHdiff (AC) VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff Defined by
Notes: 1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Voltage(i.e. DQS-DQS)
Delta TRdiff vOHdiff(AC)
O
vOLdiff(AC) Delta TFdiff
Differential Output Slew Rate Definition
Differential Output slew Rate Definition
Differential Output Slew Rate
DDR3L-800 Parameter Differential Output Slew Rate Symbol SRQdiff Min 3.5 Max 12 DDR3L-1066 Min 3.5 Max 12 DDR3L-1333 Min 3.5 Max 12
Units
V/ns
Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting
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Reference Load for AC Timing and Output Slew Rate
Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
CK, CK
DUT
DQ DQS DQS
25 Ohm VTT = VDDQ/2
Reference Load for AC Timing and Output Slew Rate
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Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Address and Control Pins
Parameter Maximum peak amplitude allowed for overshoot area. (See figure below) Maximum peak amplitude allowed for undershoot area. (See figure below) Maximum overshoot area above VDD (See figure below) Maximum undershoot area below VSS (See figure below) DDR3L-800 DDR3L-1066DDR3L-1333 Units 0.4 0.4 0.67 0.67 0.4 0.4 0.5 0.5 0.4 0.4 0.4 0.4 V V V-ns V-ns
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT) See figure below for each parameter definition
M axim um A m plitude O vershoot A rea
V olts (V)
VDD V SS
U ndershoot Area M axim um A m plitud e Tim e (ns) Add ress and Control O vershoot and U ndershoot D efinition
Address and Control Overshoot and Undershoot Definition
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Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
Parameter Maximum peak amplitude allowed for overshoot area. (See figure below) Maximum peak amplitude allowed for undershoot area. (See figure below) Maximum overshoot area above VDD (See figure below) Maximum undershoot area below VSS (See figure below) DDR3L-800 DDR3L-1066DDR3L-1333 Units 0.4 0.4 0.25 0.25 0.4 0.4 0.19 0.19 0.4 0.4 0.15 0.15 V V V-ns V-ns
(CK, CK, DQ, DQS, DQS, DM) See figure below for each parameter definition
M a x im u m A m p litu d e O v e rs h o o t A re a
V o lts (V )
VDDQ VSSQ
U n d e rs h o o t A re a M a x im u m A m p litu d e T im e (n s ) C lo c k , D a ta S tro b e a n d M a s k O v e rs h o o t a n d U n d e rs h o o t D e fin itio n
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
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Refresh parameters by device density
Refresh parameters by device density
Parameter REF command ACT or REF command time Average periodic refresh interval RTT_Nom Setting tRFC tREFI 0 C TCASE 85 C 85 C < TCASE 95 C 512Mb 90 7.8 3.9 1Gb 110 7.8 3.9 2Gb 160 7.8 3.9 4Gb 300 7.8 3.9 8Gb 350 7.8 3.9 Units Notes ns us us 1
Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3L-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 49.
Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CWL = 5 CWL = 5 Supported CL Settings Supported CWL Settings Symbol min 15 15 15 52.5 37.5 Reserved 2.5 6 5 3.3 DDR3-800E 6-6-6 max 20 -- -- -- 9 * tREFI ns ns ns ns ns ns ns 1, 2, 3, 4 1, 2, 3 Unit Notes
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG)
nCK nCK
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DDR3L-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 49.
Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CL = 7 CL = 8 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 min 13.125 13.125 13.125 50.625 37.5 Reserved Reserved 2.5 Reserved Reserved 1.875 Reserved 1.875 6, 7, 8 5, 6 < 2.5 < 2.5 3.3 DDR3-1066F 7-7-7 max 20 -- -- -- 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2, 3, 4, 5 4 1, 2, 3, 5 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 Unit Note
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
Supported CL Settings Supported CWL Settings
nCK nCK
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DDR3L-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 49.
Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6, 7 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CWL = 5, 6 CWL = 7 CWL = 5, 6 CL = 10 CWL = 7 min 13.5 (13.125)8 13.5 (13.125)8 13.5 (13.125)8 49.5 (49.125)8 36 Reserved Reserved 2.5 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.875 Reserved Reserved 1.5 Reserved 1.5 Reserved 6, 8, (7), 9, (10) 5, 6, 7 <1.875 <1.875 < 2.5 < 2.5 3.3 DDR3-1333H 9-9-9 max 20 -- -- -- 9 * tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1,2, 3,4, 6 4 1, 2, 3, 6 1, 2, 3, 4, 6 4 4 1, 2, 3, 4, 6 1, 2, 3, 4 4 1, 2, 3, 6 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 Unit Note
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
Supported CL Settings Supported CWL Settings
nCK nCK
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Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Notes: 1, The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns], rounding up to the next `Supported CL'. 3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSE LECTED. 4. `Reserved' settings are not allowed. User must program a different value. 5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Hynix DDR3 SDRAM devices support down binning to CL=7 and CL=9, tAA/tRCD/tRPmin must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3 1333H devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to DDR3-1333H or DDR3 1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
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Environmental Parameters
Symbol
TOPR HOPR TSTG HSTG PBAR
Parameter
Operating temperature Operating humidity (relative) Storage temperature Storage humidity (without condensation) Barometric Pressure (operating & storage)
Rating
See Note 10 to 90 -50 to +100 5 to 95 105 to 69
Units
Notes
3
%
o
1 1 1 1, 2
C
% K Pascal
Note: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. Up to 9850 ft. 3. The designer must meet the case temperature specifications for individual module components.
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Pin Capacitance (VDD=1.35V, VDDQ=1.35V)
2GB: HMT325R7BFR8A
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
4GB: HMT351R7BFR8A
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
4GB: HMT351R7BFR4A
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
8GB: HMT31GR7BFR8A
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
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8GB: HMT31GR7BFR4A
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
16GB: HMT42GR7BMR4A
Pin CK0, CK0 CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS
Symbol Min Max Unit pF pF pF pF
CCK CCTRL CI CIO
TBD TBD TBD TBD
TBD TBD TBD TBD
Note: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only.
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IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. * IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.
*
For IDD and IDDQ measurements, the following definitions apply: * * * * * * * "0" and "LOW" is defined as VIN <= VILAC(max). "1" and "HIGH" is defined as VIN >= VIHAC(max). "MID_LEVEL" is defined as inputs are VREF = VDD/2. Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1. Basic IDD and IDDQ Measurement Conditions are described in Table 2. Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10. IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
*
* Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
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IDD
IDDQ (optional)
VDD
RESET CK/CK CKE CS RAS, CAS, WE A, BA ODT ZQ
VDDQ
DDR3L SDRAM
DQS, DQS DQ, DM, TDQS, TDQS
RTT = 25 Ohm VDDQ/2
VSS
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above
Application specific memory channel environment
IDDQ Test Load
Channel IO Power Simulation
IDDQ Simulation
IDDQ Simulation
Correction Channel IO Power Number Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement
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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol DDR3L-1066 7-7-7 1.875 7 7 27 20 7 1KB page size 2KB page size 1KB page size 2KB page size 20 27 4 6 48 59 86 160 187 DDR3L-1333 9-9-9 1.5 9 9 33 24 9 20 30 4 5 60 74 107 200 234 Unit ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK
tCK
CL
nRCD nRC nRAS nRP nFAW nRRD
nRFC -512Mb nRFC-1 Gb nRFC- 2 Gb nRFC- 4 Gb nRFC- 8 Gb
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and Description
IDD0
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3. Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
IDD1
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
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Symbol Precharge Standby Current
Description
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2N
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2NT Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6; Pattern Details: see Table 6. Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2P0 Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit
IDD2P1
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current
IDD2Q
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD3N
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
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Symbol Operating Burst Read Current
Description
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
IDD4R
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7. Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
IDD4W
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8. Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
IDD5B
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9. Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE: IDD6
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede); IDD6ET
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Auto Self-Refresh Current (optional)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE: IDD6TC Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
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Symbol Operating Bank Interleave Read Current
Description
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
IDD7
10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
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Table 3 - IDD0 Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1,2 3,4 ... nRAS ... 1*nRC+0 1*nRC+1, 2
ACT D, D D, D PRE ACT D, D D, D PRE
CS
Datab)
0 1 1 0 0 1 1 0
0 0 1 0 0 0 1 0
1 0 1 1 1 0 1 1
1 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
00 00 00 00 00 00 00 00
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 F F F F
-
repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary
Static High
toggling
1*nRC+3, 4 ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary repeat pattern 1...4 until 2*nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
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Table 4 - IDD1 Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1,2 3,4 ... nRCD ... nRAS ... 1*nRC+0 1*nRC+1,2
ACT D, D D, D RD PRE ACT D, D D, D RD PRE
CS
Datab)
0 1 1 0 0 0 1 1 0 0
0 0 1 1 0 0 0 1 1 0
1 0 1 0 1 1 0 1 0 1
1 0 1 1 0 1 0 1 1 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
00 00 00 00 00 00 00 00 00 00
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 F F F F F
00000000 00110011 -
repeat pattern 1...4 until nRCD - 1, truncate if necessary repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary
Static High
toggling
1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MIDLEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
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Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1 2 3
D D D D
CS
Datab)
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 F F
-
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-17 28-31
repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1 2 3
D D D D
CS
Datab)
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 F F
-
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-17 28-31
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
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Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0
0
1 2,3 4 5
RD D D,D RD D D,D
CS
Datab)
0 1 1 0 1 1
1 0 1 1 0 1
0 0 1 0 0 1
1 0 1 1 0 1
0 0 0 0 0 0
0 0 0 0 0 0
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
00000000 00110011 -
Static High
toggling
6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CAS
CKE
0
0
1 2,3 4 5 6,7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
1 2 3 4 5 6 7
WR D D,D WR D D,D repeat repeat repeat repeat repeat repeat repeat
0 1 1 0 1 1 0 1 1 0 1 1 Sub-Loop Sub-Loop Sub-Loop Sub-Loop Sub-Loop Sub-Loop Sub-Loop
0, 0, 0, 0, 0, 0, 0,
0 0 1 0 0 1 but but but but but but but
0 0 1 0 0 1 BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0]
WE
CS
Datab) 00000000 00110011 -
1 1 1 1 1 1 = = = = = = =
Static High
toggling
0 0 0 0 0 0 1 2 3 4 5 6 7
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 0.2 / Feb. 2010
62
Table 9 - IDD5B Measurement-Loop Patterna)
Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0] 0 0 0
A[10]
ODT
RAS
CAS
CKE
WE
0 1
0
1.2 3,4 5...8
REF D, D D, D
CS
Datab)
0 1 1
0 0 1
0 0 1
1 0 1
0 0 0
0 0 0
0 00 00
0 0 0
0 0 0
0 0 F
-
repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Static High
toggling
9...12 13...16 17...20 21...24 25...28 29...32 2 33...nRFC-1
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.
Rev. 0.2 / Feb. 2010
63
Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 Command Sub-Loop
Cycle Number
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
0 0 0 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
0
1 2 3 4 5 6 7 8 Static High toggling 9
0 1 2 ... nRRD nRRD+1 nRRD+2 ... 2*nRRD 3*nRRD 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+2
10
11 12 13 14 15 16 17 18 19
2*nFAW+2*nRRD 2*nFAW+3*nRRD 2*nFAW+4*nRRD 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 3*nFAW+4*nRRD
ACT 0 0 1 1 0 0 00 0 0 0 RDA 0 1 0 1 0 0 00 1 0 0 D 1 0 0 0 0 0 00 0 0 0 repeat above D Command until nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 F RDA 0 1 0 1 0 1 00 1 0 F D 1 0 0 0 0 1 00 0 0 F repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 1, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 F Assert and repeat above D Command until 2* nFAW - 1, if necessary ACT 0 0 1 1 0 0 00 0 0 F RDA 0 1 0 1 0 0 00 1 0 F D 1 0 0 0 0 0 00 0 0 F Repeat above D Command until 2* nFAW + nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 0 RDA 0 1 0 1 0 1 00 1 0 0 D 1 0 0 0 0 1 00 0 0 0 Repeat above D Command until 2* nFAW + 2* nRRD - 1 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 0 Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 0 Assert and repeat above D Command until 4* nFAW - 1, if necessary
WE
CS
Datab)
00000000 00110011 -
-
0 0 0 0 0 0 0
00110011 00000000 -
0
-
0
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 0.2 / Feb. 2010
64
IDD Specifications (Tcase: 0 to 95oC)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec. The actual measurements may vary according to DQ loading cap.
2GB, 256M x 72 R-DIMM: HMT325R7BFR8A
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3L 1066 1124 1169 944 1034 318 345 944 989 354 1394 1394 2024 318 336 336 1664 DDR3L 1333 1169 1214 989 1079 318 345 989 1034 354 1529 1529 2069 318 336 336 1844 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
4GB, 512M x 72 R-DIMM: HMT351R7BFR8A
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7
Rev. 0.2 / Feb. 2010
DDR3L 1066 1304 1349 1124 1304 408 462 1124 1214 480 1574 1574 2204 408 444 444 1844
DDR3L 1333 1394 1439 1214 1394 408 462 1214 1304 480 1754 1754 2294 408 444 444 2069
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
note
65
4GB, 512M x 72 R-DIMM: HMT351R7BFR4A
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3L 1066 1484 1574 1124 1304 408 462 1124 1214 480 2024 2024 3284 408 444 444 2564 DDR3L 1333 1574 1664 1214 1394 408 462 1214 1304 480 2294 2294 3374 408 444 444 2924 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
8GB, 1G x 72 R-DIMM: HMT31GR7BFR8A
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3L 1066 1664 1709 1484 1844 588 696 1484 1664 732 1934 1934 2564 588 660 660 2204 DDR3L 1333 1844 1889 1664 2024 588 696 1664 1844 732 2204 2204 2744 588 660 660 2519 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
Rev. 0.2 / Feb. 2010
66
8GB, 1G x 72 R-DIMM: HMT31GR7BFR4A
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3L 1066 1844 1934 1484 1844 588 696 1484 1664 732 2384 2384 3644 588 660 660 2924 DDR3L 1333 2024 2114 1664 2024 588 696 1664 1844 732 2744 2744 3824 588 660 660 3374 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
16GB, 2G x 72 R-DIMM: HMT42GR7BMR4A
Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3L 1066 2564 2654 2204 2924 948 1164 2204 2564 1236 3104 3104 4364 948 1092 1092 3644 DDR3L 1333 2924 3014 2564 3284 948 1164 2564 2924 1236 3644 3644 4724 948 1092 1092 4274 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note
Rev. 0.2 / Feb. 2010
67
Module Dimensions
256Mx72 - HMT325R7BFR8A
Front
133.35
128.95 2.10 0.15 Detail A 4X3.00 0.10
SPD/TS
Registering Clock Driver
1
Detail B
Detail C
120
2X3.00 0.10
1
5.175
47.00
5.0
71.00
Back
240
121 1
Side
3.43mm max
Detail of Contacts A
1.20 0.15
Detail of Contacts B
0.80 0.05
Detail of Contacts C
2.50
0.3 0.15
2.50 0.20
0.20
3 0.1
0.3~0.1
1.00
1.50 0.10 5.00
2.50 0.20
3.80
1.27 010mm max
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 0.2 / Feb. 2010 68
9.50 17.30
30.00
512Mx72 - HMT351R7BFR8A
Front
133.35
128.95 2.10 0.15 Detail A 4X3.00 0.10
SPD/TS
Registering Clock Driver
1
Detail B
Detail C
120
2X3.00 0.10
1
5.175
47.00
5.0
71.00
Back
240
121 1
Side
3.43mm max
Detail of Contacts A
1.20 0.15
Detail of Contacts B
0.80 0.05
Detail of Contacts C
2.50
0.3 0.15
2.50 0.20
0.20
3 0.1
0.3+0.1
1.00
1.50 0.10 5.00
2.50 0.20
3.80
1.27 010mm max
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 0.2 / Feb. 2010 69
9.50 17.30
30.00
512Mx72 - HMT351R7BFR4A
Front
133.35
128.95 2.10 0.15
SPD/TS
4X3.00 0.10
Registering Clock Driver
Detail A
1
Detail B
Detail C
120
2X3.00 0.10
1
5.175
47.00
5.0
71.00
Back
240
121 1
Side
3.43mm max
Detail of Contacts A
1.20 0.15
Detail of Contacts B
0.80 0.05
Detail of Contacts C
2.50
0.3 0.15
2.50 0.20
0.20
3 0.1
0.3~0.1
1.00
1.50 0.10 5.00
2.50 0.20
3.80
1.27 010mm max
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 0.2 / Feb. 2010 70
9.50 17.30
30.00
1Gx72 - HMT31GR7BFR8A
Front
133.35
Detail B
2.10 0.15
128.95
SPD/TS
Detail A
4X3.00 0.10
Registering Clock Driver
1
120
2X3.00 0.10
1
5.175
47.00 Detail C
5.0 Detail D
71.00
Back
240
121 1
Side
Detail of Contacts A
1.20 0.15 14.90 0.4
2.50 0.20 0.20
Detail of Contacts B
Detail of Contacts C
0.80 0.05
Detail of Contacts D
2.50
3.46mm max
0.3 0.15
3 0.1
3.80
13.60
0.3~0.1
1.00
1.50 0.10 5.00
2.50 0.20
1.27 010mm max
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 0.2 / Feb. 2010 71
9.50 17.30
30.00
1Gx72 - HMT31GR7BFR8A - Heat Spreader
Front
133.75 133.35 127
42.7 20.9 6.35 3.69 5.39 8 7.74
2.786
10
14.214
120
36.7
1
7.36 46.46 80.54
33.4
33.4
119.64
57.2
Back
2.7
121
240
Side
7.19mm max
1.27 010mm max
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. 2.In order to uninstall FDHS, please contact sales administrator.
Units: millimeters
72
Rev. 0.2 / Feb. 2010
15.36
22.00
22.00 30.00
2.15
6.3
Registering Clock Driver
Registering Clock Driver
1Gx72 - HMT31GR7BFR4A
Front
133.35
Detail B
2.10 0.15
128.95
SPD/TS
Detail A
4X3.00 0.10
Registering Clock Driver
1
120
2X3.00 0.10
1
5.175
47.00 Detail C
5.0 Detail D
71.00
Back
240
121 1
Side
Detail of Contacts A
1.20 0.15 14.90 0.4
2.50 0.20 0.20
Detail of Contacts B
Detail of Contacts C
0.80 0.05
Detail of Contacts D
2.50
3.46mm max
0.3 0.15
3 0.1
3.80
13.60
0.3~0.1
1.00
1.50 0.10 5.00
2.50 0.20
1.27 010mm max
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 0.2 / Feb. 2010 73
9.50 17.30
30.00
1Gx72 - HMT31GR7BFR4A - Heat Spreader
Front
133.75 133.35 127
42.7 20.9 6.35 3.69 5.39 8 7.74
2.786
10
14.214
120
36.7
1
7.36 46.46 80.54
33.4
33.4
119.64
57.2
Back
2.7
121
240
Side
7.19mm max
1.27 010mm max
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. 2.In order to uninstall FDHS, please contact sales administrator.
Units: millimeters
74
Rev. 0.2 / Feb. 2010
15.36
22.00
22.00 30.00
2.15
6.3
Registering Clock Driver
Registering Clock Driver
2Gx72 - HMT42GR7BMR4A
Front
133.35
Detail B 2.10 0.15 Detail A 4X3.00 0.10
128.95
SPD/TS
Registering Clock Driver
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
1
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
120
2X3.00 0.10
1
5.175
47.00 Detail C
5.0 Detail D
71.00
Back
DDP Registering Clock Driver DDP DDP DDP DDP DDP
DDP
DDP
DDP
DDP
240
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
121 1
Side
Detail of Contacts A
1.20 0.15 14.90 0.4
2.50 0.20 0.20
Detail of Contacts B
Detail of Contacts C
0.80 0.05
Detail of Contacts D
2.50
3.66mm max
0.3 0.15
3 0.1
3.80
13.60
0.3~0.1
1.00
1.50 0.10 5.00
2.50 0.20
1.27 010mm max
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters
Rev. 0.2 / Feb. 2010 75
9.50 17.30
30.00
2Gx72 - HMT42GR7BMR4A - Heat Spreader
Front
133.75 133.35 127
42.7 7.74 17.2 6.1 20.9 6.35 4.06 5.16 1.1 10 2.15 36.7 8.2
2.786
Registering Clock Driver
10.1
12.02
14.214
120 240
6.8
1
7.36 46.46 80.54
33.4
33.4
119.64
57.2
Back
2.7
121
Side
7.35mm max
Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. 2.In order to uninstall FDHS, please contact sales administrator.
1.27 010mm max
Units: millimeters
76
Rev. 0.2 / Feb. 2010
15.36
22.00
22.00
Registering Clock Driver

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